The pay range below is for all roles at this level across all US locations and functions. Individual pay rates depend on a number of factors—including the role’s function and location, as well as the individual’s knowledge, skills, experience, education, and training. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.

We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI.

Location:

Hybrid, working onsite at our Santa Clara, Ca headquarters 3-5 days per week.

Job Description

We are looking for ATE Test Engineer - Contract with proven experience in developing and supporting complex silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of CPU, communication/interface protocols such as PCI-Express (Gen-4/5/6), High Speed D2D, LPDDR(4/5/6), etc. The candidate will also need work with OSAT to identify, drive test cost reduction, improve both CP and FT yield, Identify FT high yield fallout bins and enhance CP program to minimize such high FT yield fallout bins.

Basic Qualifications

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred.

• 8-year experience releasing complex SoC/silicon products to high volume manufacturing.

• Working knowledge of high-speed protocols like PCIe, LPDDRx, HBM, etc.

• Professional attitude with ability to execute on multiple tasks with minimal supervision.

• Strong team player with good communication skills to work alongside a team of high caliber engineers.

• Entrepreneurial, open-mind behavior and can-do attitude.

Required Experience

• Hands-on experience with high-speed SoC test program/hardware development on Advantest 93k test platform.

• Collaboration with design DFT team to define test strategy, create and own test plan.

• Familiar with high-speed and high power load board design techniques

• Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.

• Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – AC/DC SCAN, MBIST, DBIst, DSerDes, DDR, D2D, DIMC and other functional tests.

• Strong knowledge of lot genealogy from 2DiD bar code down to ECID in eFuse for device serial number, chiplet Id and die information.

• Expertise in production test of high speed SerDes operating at 16Gbps and higher.

• Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.

• Experience with lab equipment including protocol analyzers and oscilloscopes.

• Experience with data conversion between STDF file format into csv file format using scripts including extracting ECID reside with eFuse block

• Proficiency in modern programming languages such as C/C++, Python.

Preferred Experience

• Fluent in data processing using high level programming languages.

• Experience in running internal loopback at wafer sort as well as at FT.

• Familiarity database setup using JMP as YMS (Yield Management Tool).

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.