Open Site Navigation

Join the Entrada community

Come work with us. The companies in our network are always looking for talented, energetic, imaginative teammates who share their vision for the future.

Analog Design Engineer, Staff



Santa Clara, CA, USA
Posted on Wednesday, May 1, 2024

d-Matrix has fundamentally changed the physics of memory-compute integration with our digital in-memory compute (DIMC) engine. The “holy grail” of AI compute has been to break through the memory wall to minimize data movements. We’ve achieved this with a first-of-its-kind DIMC engine. Having secured over $154M, $110M in our Series B offering, d-Matrix is poised to advance Large Language Models to scale Generative inference acceleration with our chiplets and In-Memory compute approach. We are on track to deliver our first commercial product in 2024. We are poised to meet the energy and performance demands of these Large Language Models. The company has 100+ employees across Silicon Valley, Sydney and Bengaluru.

Our pedigree comes from companies like Microsoft, Broadcom, Inphi, Intel, Texas Instruments, Lucent, MIPS and Wave Computing. Our past successes include building chips for all the cloud hyperscalers globally - Amazon, Facebook, Google, Microsoft, Alibaba, Tencent along with enterprise and mobile operators like China Mobile, Cisco, Nokia, Ciena, Reliance Jio, Verizon, AT&AT. We are recognized leaders in the mixed signal, DSP connectivity space, now applying our skills to next generation AI.


Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week.

The role: Analog Design Engineer, Staff

What you will do:

Analog-mixed signal integrated circuit design using (but not limited to) common circuit design tools from Cadence and Synopsis. Design state of the art in-memory-compute engine for artificial intelligence accelerator and Die-Die serial interface for scale-out.

Job scope includes schematic circuit design, system level performance analysis, design test benches for simulations and verifications, guide layout engineers on layout in deep sub-micron process nodes from 7nm and below, and to optimize design and layout to achieve low power design performance over process-voltage-temperature corners and six-sigma Monte-Carlo yield analysis.

  • Independent minor layout tweaks when necessary.

  • Work with backend engineers on integration of design/layout.

  • Provide model of circuit for backend verification.

  • Participate in testboard design for silicon bring up and bench debug or characterization.

  • To build scripts for silicon bring up and test features.

What you will Bring:

  • Completed a BS/MS/PhD Preferred degree in Electrical Engineering and BS 3+/MS 1+/PHd 0+ years of related professional experience.

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.